Schedule (HW)

All deliverables are due no later than 5:00pm. Deadlines are on Tuesday and Thursday.

Milestone Time Alotted Due Date Deliverable(s)
Implement four port hard-wired switch 2 weeks 4/5 Email summarizing your progress getting the tools set up: Simulation, Synthesis, and running tests on the hardware.
4/7 Operational input arbiter (submit archive of project directory)
4/12 1. Working four-port non-learning switch (bit file and archive of project directory)
2. First version of the Hardware Design document (architecture)
3. Test summary
Implement IP router, software integration and testing of IP router 5 weeks 4/19 1. Implement basic packet counter registers
2. Add a written/drawn design of the Output Port Lookup module to your design document
4/26 1. Verification section of the Hardware Design Document
2. Ability to forward packets to/from software
3. Verify and update TTL/IP checksum
4. HW+SW: Initial Proposal of Advanced Feature
5/3 1. Verify the MAC address of all received packets
2. Lookup destination IP addresses in a lookup table. Forward matching packets to CPU instead of processing in normal forwarding path.
3. Interoperability testing section added to design document
4. HW+SW: Final Proposal of Advanced Feature
5/10 1. Implement remaining functionality, including routing and ARP tables
5/17 1. Email update on progress (1 for each team)
2. A tarball of your design (no dump files or packet_data directories please!).
Advanced Feature Development and Router Interoperation 2 weeks 5/24 1. Email update on progress (1 for each team).
2. Updated hardware design document (including advanced feature section).
5/31 6/2 1. tar.gz file of your working directory including src and verif. (but no dump files, please!)
2. Updated Hardware Design Document with your added functionality.

Stanford High-Performance Networking Group Stanford University