Schedule (HW) |
All deliverables are due no later than 5:00pm.
| Milestone | Time Alotted | Due Date | Deliverable(s) |
|---|---|---|---|
| Implement four port hard-wired switch | 2 weeks | Mon 06-Apr | Email summarizing your progress getting the tools set up: Simulation, Synthesis, and running tests on the hardware. |
| Thu 09-Apr | Operational input arbiter (submit archive of project directory) | ||
| Tue 14-Apr | 1. Working four-port non-learning switch (bit file and archive of project directory) 2. First version of the Hardware Design document (architecture) 3. Test summary |
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| Implement IP router, software integration and testing of IP router | 5 weeks | Tue 21-Apr | 1. Implement basic packet counter registers 2. Add a written/drawn design of the Output Port Lookup module to your design document |
| Tue 28-Apr | 1. Verification section of the Hardware Design Document 2. Ability to forward packets to/from software 3. Verify and update TTL/IP checksum 4. HW+SW: Initial Proposal of Advanced Feature |
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| Tue 05-May | 1. Verify the MAC address of all received packets 2. Lookup destination IP addresses in a lookup table. Forward matching packets to CPU instead of processing in normal forwarding path. 3. Interoperability testing section added to design document 4. HW+SW: Final Proposal of Advanced Feature |
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| Tue 12-May | 1. Implement remaining functionality, including routing and ARP tables | ||
| Tue 19-May | 1. Email update on progress (1 for each team) 2. A tarball of your design (no dump files or packet_data directories please!). |
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| Advanced Feature Development and Router Interoperation | 2 weeks | Tue 26-May | 1. Email update on progress (1 for each team). 2. Updated hardware design document (including advanced feature section). |
| Tue 01-Jun | 1. tar.gz file of your working directory including src and verif. (but no dump files, please!) 2. Updated Hardware Design Document with your added functionality. |
