This page lists contributions from the NetFPGA developer community. Feel free to add links to your NetFPGA contribution below. In addition to this list of projects developed specfically for the NetFPGA, see also the list of research projects on the researchers page which more generally describe networking projects implemented on FPGAs.

Classes

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Rice University: Network Systems Architecture Class

Description

The NetFPGA system was used at Rice University to teach a class on network systems architecture. It was modeled on Stanford's CS344 course where students construct an IP Router. We learned a lot about NetFPGA that is applicable towards both research and education applications, and wanted to share some of our thoughts with the user group.

Owner

Scott Rixner, Jeff Shafer

Extended Description

Contributed-Rice

University of Massachusetts Lowell: Advanced Computer Architecture Class

Description

A graduate level course on advanced topics of computer architecture and network systems at UMass Lowell. Students do course projects using NetFPGA development boards and network processor development boards.

Owner

Yan Luo

URL

Course website

Testbeds

NetFPGA Cluster at Stanford University

Description

The NetFPGA cluster consists of two racks of 40 (total) NetFPGA machines. The cluster has managed power, KVM-over-IP consoles, and a fully programmable topology of 160 Gigabit Ethernet ports.

Owner

John W. Lockwood

$ URL:

Extended Description

NetFPGA Cluster

Emulab: On-line Testbed

Description

Owner

Jay Lepreau, David Johnson, Mike Hibler

$ URL:

Supported Projects

The following projects are offically supported projects of the NetFPGA. These projects demonstrate the functionality of the card and provide useful starting points for research and teaching.

Reference NIC

Features of the NetFPGA Network Interface Card (NIC)

• Connects PC to four Gigabit Ethernet Links
• DMA efficiently transfers packets between host and network
• Hardware can be enhanced to perform in-line packet processing
• Utilizes on-board SRAM for packet buffering
• Includes a standard Linux device driver

More Information

• Specifications describe the FPGA, SRAM, DRAM, and PHY components on the NetFPGA.
• Complete Details on Wiki

IPv4 Reference Router

Features

• Four ports of Gigabit Ethernet
• Internet Protocol version 4 (IPv4)
• IPv4 packet forwarding pipeline in hardware
• Register interface to software controller
• Command Line Interface and Graphical User Interface
• Discovers Neighbors with Lightweight OSPF

More Information

• Complete Details are on the Wiki

Scone

Description

The router SCONE (Software Component Of NetFPGA) is a user level router that performs IPv4 forwarding, handles ARPs and various ICMP messages, has telnet (port 23) and web (port 8080) interfaces to handle router control, and also implements a subset of OSPF named PW-OSPF. SCONE mirrors a copy of its MAC addresses, IP addresses, routing table, and ARP table to the NetFPGA card which hardware accelerates the forwarding path.

Owner

David Erickson

URL

Gui Scone

Description

Graphical User Interface for the reference router. Shows the routing and arp tables along with statistics (including throughput, and various counters).

Owner

Jad Naous

URL

Hardware Accelerated Linux Router

Features

• Hardware Acceleration to unmodified Linux System
• Mirrors Linux Routing and ARP tables into NetFPGA reference router
• Supports Manual entries using arp or route commands
• Can run alongside a standard routing daemon, such as XoRP, or Zebra/Quagga

More Information * [[NetFPGA/OneGig/Guide#Router_Kit_Walkthrough][Complete Details are in the Guide] * [[http://forum.netfpga.org/forumdisplay.php?f=12][Forum Discussion Board]

Router Buffer Sizing

Description

Owner

URL

DRAM Queue Test

Features

• Drive DDR2 DRAM on NetFPGA board for packet buffering
• SRAM is free to use as other purposes
• Four ports of Gigabit Ethernet
• Internet Protocol version 4 (IPv4)
• IPv4 packet forwarding pipeline in hardware
• Register interface to software controller
• Command Line Interface and Graphical User Interface
• Discovers Neighbors with Lightweight OSPF

More Information

• [[NetFPGA/OneGig/DRAMQueueTest][Complete Details are on the Wiki]

User Contributed Projects

User contributed projects are provided by the users and are not supported by the NetFPGA team. If there are problems or questions about the following projects please contact the project owners.

Packet generator

Description

A simple "packet generator/capture" system that uses the NetFPGA to transmit sequences of packets. In this design, the packet sequence is loaded into SRAM and the NetFPGA replays the sequence from SRAM. Sequences can include delays between packets or can simply be replayed at line rate. The design supports separate sequences on each of the 4 ports. The design also supports iterating over the sequences any number of times.

Owner

Glen Gibb

URL

Packet generator wiki page

Router buffer sizing (University of Toronto)

Description

In this work, we set up a test-bed of several Dell Power Edge 2950 servers each equipped with NetFPGA boards to perform experimental studies on router buffer sizing. With NetFPGA as the router, one can control the buffer sizes with high precision, based on the number of packets or bytes, and without the worry of hidden buffers in the system. We have also added a module to the NetFPGA-based router to collect accurate buffer occupancy time-series, and to accurately measure the bottleneck link's utilization and loss rate. We have also written scripts to automatically set up a test-bed of NetFPGA routers. The scripts discover the network topology, set up the ARP tables, configure IP addresses, and routing in the test-bed.

Owner

Yashar Ganjali: http://www.cs.toronto.edu/~yganjali/

URL

http://www.cs.toronto.edu/~yganjali/research/projects/bsizing/

PTP: Precision Time Protocol

Description

This project implements PTP standard by using NetFPGA platform. PTP is a simplified version of "IEEE 1588 standard which is a protocol designed for synchronizing real time clocks in the node of a distributed system that communicates using a network" [1]. In this project required changes has been made in NetFPGA's reference_router design in order to support PTP. In this document first we explain briefly how PTP works. In the following the software and hardware parts of the design are explained. For those people which are interested in using PTP router for clock synchronization, a chapter is designated to explain how to setup the nodes and configure the system. Finally some intermediate results are presented which are achieved using the PTP router for synchronization.

Owner

Sara Bolouki, Peter Pawlowski, Jad Naous.

URLs

PTP System?

1- 1588 software?

2- Changes in the router to support 1588

3- Steps of adding registers

3- Software hardware interface

4- Experiment results

Click Any-to-Any test (ICSI)

Description

Any to Any test using click, http://www.icsi.berkeley.edu/~nweaver/ntest.tar

Owner

Nicholas Weaver, ICSI

Summary

This test invokes Click to run an "any to any" send test. It first sends a total of 16 ethernet Broadcast packets, with the SRC mac as CA:FE:BA:BE:00:p# and the dest MAC as FF:FF:FF:FF:FF:FF, ethertype 0x890F (an unassigned ethertype). It will then repeat forever, sending a packet from a pseudo-random SRC to a different pseduo-random DST, ethertype 0x890F.

Extended Description

Contributed-Any_to_Any

Deficit Round Robin (DRR)

Description

Owner

Peyman Kazemian & Drew Mazurek

Project Wiki Page

DRR-NetFPGA

RCP: Rate Control Protocol

Description

Implementation of the RCP protocol on NetFPGA (http://yuba.stanford.edu/rcp/). This implementation consists of three parts: RCP datapath implemented on the NetFPGA, RCP Control Path (user-level program), and RCP end-host kernel patch.

Owner

Sara Bolouki, Nandita Dukkipati, Jiang Zhu

URL

RCP router wiki page

Live CD for OpenSuSE

Description

Live CD based on openSuSE 10.3 that has OpenFlow and NetFPGA binaries installed

Owner

Jad Naous

URL

LiveCD

BORPH

Description

Port of the BORPH operating system kernel for the NetFPGA platform.

Owner

Brandon Hamilton

URL

BORPH wiki page

Add your project here

Description

We encourage you to list and link your project here. To edit this page, you must be member of the NetFPGA Trash.NetFPGA_OneGigBetaPlus program. Once registered, just cut and paste this text block above this line and edit this Wiki page.

Owner

Add a link to My Name

URL

Add a link to the a project website that has details about the work (publications, project description, or Wiki page)