The Parallel Shared Memory Router
Summary - Routers which give 100% throughput
Intuition for Theorem
2
N=3 port router
Summary - Routers which give delay guarantees
An Example
Packet
buffers for a 40Gb/s line card
Can’t we just use lots of DRAMs in parallel?
Works fine if there is only one FIFO queue
In practice, buffer holds many FIFOs
Parallel Packet Buffer
Hybrid Memory Hierarchy
Why do we need a large
SRAM?
Q = 4, w = 3, b = 3
Summary of
Contributions
Covered in this talk
Summary of
Contributions
Not covered in this talk
Summary of
Contributions
Not covered in this talk