| Works fine if there is only one FIFO queue |
| 40B |
| 320B |
| 320B |
| 320B |
| Write Rate, R |
| Read Rate, R |
| 40B |
| 40B |
| 40B |
| 40B |
| 40B |
| 40B |
|
|
|
| One 40B packet |
||
| every
8ns |
||
|
|
|
| One 40B packet |
||
| every
8ns |
||
|
|
|
| Buffer Manager |
||
| (on
chip SRAM) |
||
|
|
| Scheduler |
|
| Requests |
|
|
|
|
| Aggregate
320B for the queue in fast SRAM and read |
||
| and write to all
DRAMs in parallel |
||
| 29 |