| In practice, buffer holds many FIFOs |
| 1 |
| 320B |
| 320B |
| 320B |
| 320B |
|
|
|
|
|
|
|
| e.g. |
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| v | In an IP Router, |
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| Q might be 200. |
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| v | In an ATM switch, |
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| Q might be 106. |
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|
|
|
|
| We
don’t know which |
|||
| head of
line packet |
|||
| the
scheduler will |
|||
| request next? |
|||
| 2 |
| Q |
| 320B |
| 320B |
| 320B |
| 320B |
| 40B |
| 320B |
| 320B |
| 320B |
| Write Rate, R |
| Read Rate, R |
| ?B |
| ?B |
| 320B |
| 320B |
|
|
|
| One 40B packet |
||
| every
8ns |
||
|
|
|
| One 40B packet |
||
| every
8ns |
||
|
|
|
| Buffer Manager |
||
| (on
chip SRAM) |
||
|
|
| Scheduler |
|
| Requests |
|
| 30 |