Theorem 5
	v Problem: Ø What is the minimum size of the SRAM so that every packet is available in the SRAM within a bounded pipeline latency when requested?
	v Theorem 5: (necessity and sufficiency) Ø An SRAM cache of size Qw = Q(b – 1) bytes is both necessary and sufficient if the pipeline latency is Q(b – 1) + 1 time slots.
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