Parser generator
A parser generator is a tool for generating parser for parsing network packets. It takes several parameters as input, such as a parse graph, and produces synthesizable Verilog.
Download
The parser generator is located on github:
Prerequisites
The parser generator uses the Genesis chip generator to perform generation. Information about obtaining Genesis can be found here: http://genesis2.stanford.edu/
The generator produces synthesizable SystemVerilog. Simulation, synthesis, and place-and-route require the use of third party tools. The tools used for testing during development were:
- Synopsys VCS Simulator
- Synopsys Design Compiler
- Synopsys IC Compiler